Various different current mirrors are known and a simple current mirror 1 is shown in FIG. 1. The simple current mirror 1 comprises first and second n-type field effect transistors (FETs) 2 and 4 which are matched. The source of each of the FETs 2 and 4 is connected to ground. The gates of the two FETs 2 and 4 are connected to one another. The gate and the drain of the first FET 2 are connected to each other. An input node 13 is connected to the drain of the first transistor 2.
The input node 13 receives an input current Iin. This input current Iin gives rise to the voltage at the input node 13. When the voltage is high enough, the first and second transistors 2 and 4 will conduct and the first transistor 2 will source a current equal to Iin. The output of the current mirror 1 is taken from output node 14 which is connected to the drain of the second transistor 4. If the voltage on the output node 14 is above the saturation voltage, the second transistor 4 will source a current lout similar to or equal to Iin. The input current Iin has thus been "mirrored".
The same voltage at the first node 13 will provide the gate voltages for the first and second transistors 2 and 4.
The voltage required at the output node must be at least equal to the saturation voltage for the input current to be mirrored. In saturation, the following equation applies: EQU Vds sat=Vgs-Vt=.DELTA.V
where Vds sat=the saturation voltage
Vgs=gate-source voltage PA1 Vt=threshold voltage. PA1 (i) Critical voltage--that is the minimum required voltage at the output node to obtain current mirroring. PA1 (ii) the incremental output resistance ##EQU1## PA1 (iii) where the output resistance is high, the accuracy of the mirroring is important. If the output resistance is low, the output current varies with the output voltage and the concept of accuracy is of limited use. PA1 (Vgs-Vt) for the third transistor 54=2.times.(Vgs-Vt) for the first transistor 50. PA1 (Vgs-Vt) for the second transistor 52+(Vgs-Vt) for the fourth transistor=2.DELTA.V as Vgs-Vt is the same for first, second and fourth transistors.
There are features which can be used to measure the effectiveness of the current mirror:
where Vout is the voltage at the output node and lout is the current at the output node.
The current mirror of FIG. 1 has a low critical voltage of .DELTA.V, a reasonable output resistance .DELTA.V/Iout.
However, the accuracy is not particularly good. In particular the current mirror shown in FIG. 1 may not be accurate enough for certain applications. With the current mirror shown in FIG. 1, fluctuations in the voltage on the output node 14 can effect the ability of the current mirror 1 accurately to mirror the input current Iin to the output. In particular, if Vout does not equal the voltage at the input node, there will not be perfect current mirroring.
The cascode current mirror 19 has therefore been proposed and this is shown in FIG. 2. The cascode current mirror 19 comprises two matched pairs of n-type FETs. The first and second pairs of FETs do not need to be the same. The first pair of transistors 16 and 18 have the same configuration as the first and second transistors shown in FIG. 1. In other words, the source of each of these transistors 16 and 18 is connected to ground and the gates of the two transistors 16 and 18 are connected together. The gate and the drain of the first FET 16 are connected together. The drain of the first transistor 16 is connected to the source of the third transistor 24.
The gates of the third and fourth transistors 24 and 26, making up the second pair of transistors, are connected to one another. The gate and drain of the third transistor 24 are connected. A current Iin is input via a first node 30 connected to the drain of the third transistor 24. The drain of the second transistor 18 is connected to the source of the fourth transistor 26. The output current Iout is taken from an output node 31 which is connected to the drain of the fourth transistor 26.
When a current Iin is received via the first node 30, the third and fourth transistors 24 and 26 will conduct if the voltage is high enough. The current is therefore conducted through the third transistor 24. If the voltage on the drain and gate of the first transistor 16 is large enough, the first and second transistors 60 and 80 will conduct. The arrangement of FIG. 2 allows the output current Iout at the output node 31 to be similar to or equal to the input current Iin. This is because a near constant voltage is maintained for the second transistor 18 by the fourth transistor 26. The drain voltages of the first and second transistors are kept at very similar levels. If the drain voltages differ, then the quality of the current mirroring decreases. Changes in the output voltage do not effect the drain voltage of the second transistor 18 as much as in the arrangement of FIG. 1. This is due to the presence of the fourth transistor 26.
However, because there are two additional transistors in the cascode mirror, as compared to the simple current mirror shown in FIG. 1, the critical voltage required for the cascode mirror to operate is much larger than for the simple current mirror of FIG. 1. The critical voltage=.DELTA.V (for the second transistor 18)+Vgs (for the fourth transistor)=.DELTA.V+(.DELTA.V+Vt)=2.DELTA.V+Vt. This is assuming that all four transistors have the same characteristics. Rout is good as is the accuracy.
The Wilson current mirror is similar to the cascode current mirror of FIG. 2 but only has three transistors. This has the same problems as the cascode current mirror. The Wilson current mirror would require a critical output voltage similar to that required by the cascode current mirror.
A third known arrangement is called the scaled Ids current mirror 49 and is shown in FIG. 3. Ids is the drain source current. The scaled Ids mirror 49 resembles the cascode current mirror and has four N-type transistors. The first and second transistors 50 and 52 constitute the first pair and the third and fourth transistors 54 and 56 constitute the second pair. The first and second transistors 50 and 52 are a matched pair. Whilst the third and fourth transistors 54 and 56 may be a matched pair, as will be discussed hereinafter, it is preferred that these transistors are not in fact matched. The first and third transistors 50 and 54 are on the input side whilst the second and fourth transistors 52 and 56 are on the output side.
In contrast to the cascode mirror shown in FIG. 2, each of the input transistors, the first and third transistors 50 and 54, is arranged to receive its own input current. The first transistor 50 receives via its drain a first input current Iin1. The third transistor is arranged to receive a second input current Iin2, also via its drain. The sources of the first and second transistors 50 and 52 are connected to ground. The gates of the first and second transistors 50 and 52 are connected to each other. The gate of the first transistor 50 is connected to its drain.
The source of the third transistor 54 is connected to ground. The gate of the third transistor 54 is connected to the gate of the fourth transistor 56 and to the drain of the third transistor 54. The third transistor is not in series with the first transistor, as in the cascode current mirror. Rather, the source of the third transistor 54 is connected directly to ground. This means that the voltage required at the drain of the third transistor is smaller than that required on for example the drain of corresponding transistor of the cascode current mirror, for similarly sized transistors. This reduces the minimum voltage required at the output.
The current mirror 49 shown in FIG. 3 provides a good performance when the current density in the first transistor 50 is four times that to the current density in the third transistor 54. In other words, the ratio of the width to length of the channel in the first transistor is four times the ratio of the width to the length of the channel in the third transistor 54. The first, second and fourth transistors 50, 52 and 56, in this particular embodiment, share the same characteristics. This gives rise to the following equation:
The critical voltage for the output node 59 is then
This provides better performance than the cascode current mirror in that the critical voltage is smaller. The drain voltage of the second transistor 52 is set by the third transistor 54 and the gate voltage is set by the first transistor 50. The gate voltage of the fourth transistor 56 can be reduced without disturbing the drain voltage of the second transistor 52. However, the arrangement shown in FIG. 4 has the disadvantage that two equal or scaled input currents are required. This may be undesirable in certain applications. The accuracy is reduced but Rout is good.